Produits

IP CATALOG

NIOSII_SC Processor

NIOSII_SC is the safety critical version of the NIOSII processor from Intel (formerly Altera). This IP is targeting the airborne electronic applications and It has been developed in compliance with the requirements and objectives of the DO-254 DAL A. t has the following technical characteristics:

  • Fully compatible with Fast Nios II
    • Same instruction set architecture
    • Cycle accurate behavior compatibility
  • Full 32-bit instruction set & data-path
  • 31-bit address space
  • Support of internal instruction cache
  • 6 stage execution pipeline
  • 32 external interrupt sources
  • Support of external custom instruction interface
  • Interface with external hardware-assisted debug module
  • Additional NIOSII_SC capacities for safety requirements
    • Embedded RAM protection against SEU
    • Invalid instructions and opcodes monitoring

Processor Peripherals

  • Serial Peripheral Interface (SPI)
  • Real Time Clock (RTC)
  • Universal Asynchronous Receiver Transmitter (UART)
  • Watchdog Timer (WDG)
  • Parallel Input/output (PIO)

ARINC 429 Transmitter

The ARINC 429 TX is a soft IP for a single transmitter for serial communication in airborne applications. It has been developed in compliance with the requirements and objectives of the DO-254 DAL A. As a COTS IP, it can be instantiated as many times as required within a SoC to have multiple ARINC 429 transmitters. This IP has the following technical characteristics:

  • User configurable data transmission bit rate: high speed or low speed
  • 32-bit parallel user interface to write the frame to be transmitted
    • Frames are stored in a FIFO within the ARINC429-TX IP
    • FIFO size is configurable by the user (from 2 to 512 words)
  • Parity bit calculation
  • Frame encoding and transmission through data_high and data_low outputs according to the ARINC429 standard.

ARINC 429 Receiver

The ARINC 429 RX is a soft IP for a single receiver for serial communication in airborne applications. It has been developed in compliance with the requirements and objectives of the DO-254 DAL A. As a COTS IP, it can be instantiated as many times as required within a SoC to have multiple ARINC 429 receivers. This IP has the following technical characteristics:

  • Automatic detection of the ARINC429 bus bit rate: high speed or low speed.
  • Decoding of the serially received data through data_high and data_low inputs
  • Received frames format check (Bit rate, Frame width, Inter-frame gap) and parity errors checks
  • Errors are highlighted to the user through external status/flags outputs and erroneous frames are discarded
  • Error free frames are stored in a FIFO within the ARINC429-RX IP
    • FIFO size is configurable by the user (from 2 to 512 words)
  • User performs read accesses to the FIFO through 32-bit interface to retrieve the received frames

CAN MAC ARINC 825

The CAN MAC ARINC 825 is a soft IP fully compliant with BOSCH CAN 2.0 B and ARINC spec 825 standards. It has been developed in compliance with the requirements and objectives of the DO-254 DAL A. As a COTS IP, it can be instantiated as many times as required within a SoC to have multiple CAN MAC. This IP has the following technical characteristics:

  • Support of all frames types specified in the standards and their bitstreams coding
  • Arbitration logic and message transfer validation
  • Support of error detection and signaling
  • Fault confinement and bus state management
  • Error containment and bus off management
  • Bit timing and bus status management

Single Precision Floating Point Unit

Implemented according to the IEEE standard 754 for normalized single-precision floating-point numbers. The IP is optimized for performance and HW resources usage and it supports the following operations:

  • Arithmetic: Add, Subtract, Multiply, Divide
  • Comparison: Greater or equal, Smaller or equal, Greater, Smaller, Equal, Not equal
  • Conversion: Integer to float, Unsigned integer to float, Float to integer, Float to unsigned integer

The supported rounding mode is round-to-nearest-even

Dedicated output flag interface to highlight the occurrence of the following events:

  • An input operand is Not a Number
  • An input operand is ± infinite
  • The result is ± Underflow
  • The result is ± Overflow
  • The result is Not a Number
  • The result is Zero
  • The result is positive or negative.
  • A division by zero

It has a simple user interface and can be used also as a HW accelerator for processor’s custom instructions

For flexibility, all the operations are configurable to be active or not within the IP.

Double Precision Floating Point Unit

Implemented according to the IEEE standard 754 for normalized double-precision floating-point numbers. The IP is optimized for performance and HW resources usage and it supports the following operations:

  • Arithmetic: Add, Subtract, Multiply, Divide
  • Comparison: Greater or equal, Smaller or equal, Greater, Smaller, Equal, Not equal
  • Conversion: Integer to double float, Unsigned integer to double float, Double float to integer, Double float to unsigned integer

The supported rounding mode is round-to-nearest-even

Dedicated output flag interface to highlight the occurrence of the following events:

  • An input operand is Not a Number
  • An input operand is ± infinite
  • The result is ± Underflow
  • The result is ± Overflow
  • The result is Not a Number
  • The result is Zero
  • The result is positive or negative.
  • A division by zero

It has a simple user interface and can be used also as a HW accelerator for processor’s custom instructions

For flexibility, all the operations are configurable to be active or not within the IP.

DDR3 Memory Controller

Serial Flash Nor Controller

DO-254 Development Process

For safety critical IP design, HCell development its own development life process and life cycle data fully compliant with the requirements and objectives of DO-254 standard up to DAL A:

  • Plans
    • IP Design Assurance Plan
    • IP Configuration Management Plan
    • IP Assurance Plan
  • Standards
    • Design Standards
    • Validation & Verification standards
  • Design Data
    • IP Requirements Specification
    • IP Conceptual Design
    • IP Detailed Design
  • Verification Data
    • IP Verification Strategy
    • IP Verification Procedures
    • Verification test benches
    • IP Verification Results
  • Traceability Data
  • IP Configuration Index
  • IP Process Assurance Records
  • IP Accomplishment Summary